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AT45CS1282 [Preliminary]
commands previously mentioned. If this pin and feature are not utilized it is recom-
mended that the WP pin be driven high externally.
RESET: A low state on the reset pin (RESET) will terminate the operation in progress
and reset the internal state machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET pin. Normal operation can
resume once the RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions
on the RESET pin during power-on sequences. If this pin and feature are not utilized it is
recommended that the RESET pin be driven high externally.
READY/BUSY: This open drain output pin will be driven low when the device is busy in
an internally self-timed operation. This pin, which is normally in a high state (through
an external pull-up resistor), will be pulled low during programming/erase operations,
compare operations, and page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
8-BIT PORT SUPPLY VOLTAGE (VCCP AND GNDP): The VCCP and GNDP pins are
used to supply power for the 8-bit input/output pins (I/O7-I/O0). The VCCP and GNDP
pins need to be used if the 8-bit port is to be utilized; however, these pins s hould be
treated as “don’t connects” if the SER/BYTE pin is not connected or if the SER/BYTE pin
is always driven high externally.
Power-on/Reset State
System
Considerations
When power is first applied to the device, or when recovering from a reset condition, the
device will default to Mode 3. In addition, the output pins (SO or I/O7 - I/O0) will be in a
high impedance state, and a high-to-low transition on the CS pin will be required to start
a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every
falling edge of CS by sampling the inactive clock state. After power is applied and V CC is
at the minimum datasheet value, the system should wait 20 ms before an operational
mode is started.
The RapidS serial interface is controlled by the serial clock SCK, serial input SI and chip
select CS pins. The sequential 8-bit Rapid8 is controlled by the clock CLK, 8 I/Os and
chip select CS pins. These signals must rise and fall monotonically and be free from
noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges
and cause improper operation of the device. The PC board traces must be kept to a
minimum distance or appropriately terminated to ensure proper operation. If necessary,
decoupling capacitors can be added on these pins to provide filtering against noise
glitches.
As system complexity continues to increase, voltage regulation is becoming more
important. A key element of any voltage regulation scheme is its current sourcing capa-
bility. Like all Flash memories, the peak current for DataFlash occur during the
programming and erase operation. The regulator needs to supply this peak current
requirement. An under specified regulator can cause current starvation. Besides
increasing system noise, current starvation during programming or erase can lead to
improper operation and possible data corruption.
11
3447A–DFLSH–2/04
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